The present invention relates to a current sense circuit for sensing memory devices, and more particularly, to a circuit suitable for fast response operations of large signals.
The current sense circuit is as well known, good for sensing small currents from signal sources which have large inherent capacitances. This is because the current sense circuit has a low input impedance and can provide a constant voltage for the signal source. By means of providing a constant voltage across the inherent capacitance of the signal source, it can avoid current being contributed by the capacitance so that the true signal current can be picked up by the sense circuit.
One of the conventional current sense circuits is as shown in FIG. 6 which comprises a current source type input to the sense circuit at 14', an impedance transfer circuit 17' composed of a sense transistor M1 and an inverting amplifier A1, a load 21' connected between the drain of the transistor M1 and a positive supply terminal Vcc and a two-stage comparator 23'. The output 19' of the impedance transfer circuit 17' is coupled to the inverting terminal of the two-stage comparator 23' so as to be compared with a first reference voltage 22' which inputs from a non-inverting terminal of the comparator 23'.
The current source input 14' is coupled to an inverting terminal of the amplifier A1 and a second reference voltage 18' is input to the amplifier A1 from a non-inverting terminal thereof. The transistor M1 is served as a source follower. The output of the amplifier A1 is connected to a gate of the transistor M1 and there is a negative feedback loop between the amplifier and the transistor so that at the point 15', there is a very low input impedance and a constant terminal voltage, which approximately equals the second reference voltage 18' that is provided. In a real circuit, the amplifier A1 may be an amplifier with a single input terminal. In this case, the reference voltage 18' is deemed as a virtual reference voltage.
The impedance transfer circuit 17' has a high impedance output on the point 19' and the current at the point 19' equals the current flowing to the current source input 14'. Therefore, by measuring the current at the point 19', it is possible to measure the current of the current source 14'. The comparator 23' then compares the current level (or voltage level output Vout) and the first reference current level (or the first reference voltage level 22') to provide a logic level output 24' for the sense circuit.
However, when the prior sense circuit is applied to sense the current of the memory devices, several problems occur. In such case, the current source 14' is a memory cell and the sense circuit will be influenced not only by the small signal response, but also by the large signal response. Such a prior sense circuit is normally connected to the memory cell via bit line multiplexers and bit lines and the selected bit lines should undergo voltage level transition caused by the action of an address decoder. In the transition period, the current sense circuit of FIG. 6 can pick up combinations of signals, especially the current contribution of the inherent capacitance of the signal source, rather than the true signal current. In this case, the inherent capacitance of the signal source is a parasitic capacitance of the bit line and the current picked up by the sense circuit is mostly the charge current for the parasitic capacitance, which is much larger than the true signal current which the circuit intends to detect.
To explain the disadvantages of the prior art, the following discloses a conventional read only memory cell array and multiplexer in accompanied with FIG. 5.
As shown in FIG. 5, the memory cell array includes word lines 5, bit lines 6 and a number of cell transistors such as those 1, 2, 3 and 4. The multiplex includes X multiplexers 7, 8 and Y multiplexers 9, 10, 11 and 12. The arrow numbered by 14 in FIG. 5 connects to the current source 14' in FIG. 6 (14" in FIGS. 8 and 14 in FIG. 1) representing that the output of the memory cell are input into the current sense circuit. Each of the cell transistors represent some bit of data. Take the cell transistor 3 as an example, if the transistor 3 is a normal transistor, the bit is 1 and if the transistor is an always-off transistor (e.g. by means of being programmed by boron implantation), the bit is 0. To access the bit represented by the transistor 3, XA 7 is set to low, XB 8 is set to high; WO2 5 is set to high, other word lines 5 except WO2 are set to low; YM1 is set to high, YG1 is set to high, and YG2 is set to low. In this way, BL2 (a second bit line) and source/drain diffusions S2B and S3A are switched to the terminal 14; BL3 (a third bit line) and source/drain diffusion S3B are switched to ground; BL1 (a first bit line) and source/drain diffusion S2A are switched to the terminal 13.
In order to determine whether the transistor 3 is a normal transistor or an always-off transistor, the sense circuit provides a bit line voltage of 1.5 V to the bit line, hence a voltage of 1.5 V shall be applied to the transistor at S3A. At this time, S3B is connected to the ground. If the transistor 3 is a normal transistor, it will be turned on and a current will flow therefrom. If the transistor 3 is an always-off transistor, then no current will be flowing from the transistor 3. Accordingly, the sense circuit is used to detect and quantize the current level into logic 1 or 0. In the case of the above, since BL1 and S2A are driven to 1.5 V via the terminal 13, no current will pass through the transistor 1, that is, only the transistor 3 is tested.
The equivalent circuit or the memory cell which connects to a normal transistor is as shown in FIG. 7 which comprises a cell current source Ic and a stray capacitance C.sub.O and a resistance R.sub.O respectively connected in parallel with the cell current source Ic. If the memory cell is connected to an always-off transistor cell, the equivalent circuit of the memory cell can be obtained by removing the elements R.sub.O and I.sub.c from FIG. 7, which means that the equivalent circuit thereof is equivalent to the bit line stray capacitance C.sub.O. For fast detection, the voltage of selected bit line has to be increased to a higher potential of about 1.5 V from ground potential. When an always-off transistor is used, the charge of the bit line capacitance will dominate the current being picked up by the sense amplifier, such that the correct data is unavailable. Moreover, in order to achieve faster access time for the memory chip, the transition time of the bit line should be as short as possible. However, due to the presence of the load 21' as shown in FIG. 6, the access time is limited. As a result, the sense circuit in FIG. 6 is not suitable for fast operation with bit line voltage transition.
Another prior art of the sense circuits which is intended to solve the problem of the load by restricting the response of the large signals (i.e., the voltage of the bit line range from 0 to 1.5 V) is as shown in FIG. 8. To help to explain the operation of the sense circuit of FIG. 8, the same elements as those shown in FIG. 6 are referenced by the same numbers. As shown in the figure, the circuit further comprises a second transistor M2 disposed between the inverting amplifier A1 and the transistor M1. Further, a Miller's capacitance C.sub.m is connected between a gate of the second transistor M2 and a drain of the first transistor and a stray capacitance C.sub.L is connected between the drain of the first transistor M1 and a ground. The source of the transistor M2 is connected to the connecting point of the source of the transistor M1 and the current source 14" for speeding up the response of the large signals. In the case of detecting small signals, part of the current from the current source 14" bypasses through the transistor M2 such that the current I1 in FIG. 8 is smaller than that in FIG. 6. When the current I1 becomes smaller, the voltage drop across the load 21" decreases, thereby limiting the voltage martin of the sense circuit. During operation, current I1 and current I1 are switched on simultaneously and the current I2 is large than I1, so that if the load 21" does not become larger, the sense margin will become smaller. By increasing the impedance of the load 21", the sensing margin will be retained, it will cause the following disadvantages:
(1) The higher the impedance of the load 21" is the larger the voltage gain from terminal 14" to the output terminal 19" becomes, the noise immunity becomes poorer, which results in an unstable operation point of the transistor M1; and PA1 (2) The higher the impedance of the load 21" is, the smaller the current I1 through the load becomes, thus inevitably causing the small signal response to slow down.
The current through the transistor M2 can be compensated by enlarging the size of the transistor M2, but the larger the transistor M1 is, the larger the Miller's capacitance C.sub.m becomes, and hence the stray capacitance C.sub.L will be, which further degrades the response speed of the small signals.